1. Technical Field
The present invention relates to a backup line allocation apparatus, a memory repairing apparatus, a backup line allocation method, a memory manufacturing method, and a recording medium. In particular, the present invention relates to a backup line allocation apparatus that determines which fail lines have backup lines allocated thereto in a memory, such as a semiconductor memory, provided with a plurality of backup lines.
2. Related Art
A conventional semiconductor memory has storage cells arranged in a two-dimensional matrix. When manufacturing such a semiconductor memory, the memory is desirably designed such that all of the storage cells operate properly. However, since recent semiconductor memories have an extremely large number of storage cells, it is difficult for all of the cells to operate properly.
One known method for dealing with this problem involves forming a semiconductor memory having a prescribed number of backup lines for address lines in rows and columns in the matrix of storage cells. In such a semiconductor memory, the address lines that have defective storage cells, known as “fail bits,” are replaced with backup lines to repair a semiconductor memory having defective storage cells, as in, for example, Japanese Patent Application Publication No. 2-24899.
There is a limit, however, to the number of backup lines that can be formed in a semiconductor memory. Therefore, if the backup lines are not appropriately allocated to the address lines that have fail bits, not all of the fail bits can be repaired. Recent semiconductor memories have a huge number of address lines, and therefore it takes an extremely long time to find the proper backup line allocation that allows all of the fail bits to be repaired. Therefore, a technique is desired to efficiently detect the allocation of backup lines that allows all of the fail bits to be repaired.